パリティエラー発生メモリ素子の識別方式

Identification system for parity error occured memory element

Abstract

(57)【要約】 【目的】 メモリの1データを形成する複数のメモリ素 子のうち、パリティエラーの発生したメモリ素子を識別 できるようにしたパリティエラー発生メモリ素子の識別 方式を提供する。 【構成】 1データ内の各メモリ素子毎に設けられ、そ のメモリのパリティを生成し且つパリティエラーを検出 するパリティ生成チェック回路2と、各メモリ素子毎の パリティエラーの有無を識別するレジスタ回路7とを備 えた。
PURPOSE: To easily identify a memory element with an error by providing a parity generation check circuit detecting the parity error and a register circuit identifying the presence or absence of the parity error for the respective memory elements. CONSTITUTION: When a micro computer 3 outputs the address of a read destination to an address bus 11, an address decoder 15 decodes a signal on the address bus 11, generates a memory selection signal 16 and inputs it to a data memory 4 and a parity memory 5. The micro computer 3 outputs a read signal 18, reads data from the data memory 4 and reads a parity signal from the parity memory 5. A parity generation check circuit 2 checks the parity for the respective memory elements by using data on a data bus 12 and the respective parity signals. Furthermore, the micro computer 3 reads the presence or absence of the parity error of the respective memory elements stored in the register circuit 7. COPYRIGHT: (C)1993,JPO&Japio

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    JP-2015011385-AJanuary 19, 2015富士通セミコンダクター株式会社, Fujitsu Semiconductor LtdMonitoring circuit, semiconductor device, and memory monitoring method